III-V-on-Si transistor technologies: Performance boosters and integration

In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the approach must be tailored intended application to maximize performance, functionality minimize cost. also highlight performance boosters such as heterostructure channel stacks, which offer increased carrier mobility towards improved RF RF-CMOS performance. Recent tunneling field-effect transistors (TFETs) have enabled TFET architecture process module, allowing dense MOSFETs on same chip an extremely low-power CMOS technology. Finally, emerging applications devices at cryogenic temperatures, where there is rising need electronics support scaling of quantum computers. The unique properties III-V, their high band gap engineering make them highly suitable application.